The present invention relates to a non-volatile flash memory that can reprogram stored information by electrical erasure and programming and to a microcomputer incorporating the flash memory. More specifically, this invention relates to a technology suitably applied to a method of supplying erasing and programming voltages to the flash memory.
[0002]
Japanese Patent Laid-Open No. 161469/1989 describes a microcomputer that mounts on a single semiconductor chip an EPROM (erasable and programmable read only memory) or EEPROM (electrically erasable and programmable read only memory) as a programmable non-volatile memory. An on-chip non-volatile memory for such a microcomputer holds programs and data.
The EPROM erases stored information by ultraviolet rays and thus cannot be programmed unless it is removed from the mounted system. The EEPROM can erase or write data electrically and thus can change its stored information while it is mounted on the system. But because memory cells forming the EEPROM require selection transistors in addition to memory elements such as NMOS (metal nitride oxide semiconductor), the EEPROM is about 2.5 to 5 times as large as the EPROM, occupying a relatively large chip area.
[0003]
Japanese Patent Laid-Open No. 289997/1990 describes whole information erasing type EEPROM, which can be taken to be identical with the flash memory mentioned in this specification. The flash memory can change its stored information by electrical erasing and programming and form the memory cell with one transistor, and, like the EPROM, has the function of electrically erasing the whole memory cells or a block of memory cells in one operation. Thus, the flash memory can change its stored information while in the system-mounted (or device-mounted) state and, by its block erasing function, can shorten the re-programming time and also contribute to reducing the chip occupying area.
[0004]
Among the conventional methods of supplying erasing and programming potentials to the flash memory there are two methods. One is to provide, in addition to an ordinary power supply voltage terminal, a second terminal for a power supply voltage higher than the first one. The other method provides a boost circuit in the chip to generate an erasing and programming voltage Vpp such as 12 V from the ordinary power supply voltage Vcc such as 5 V.
For example, Japanese Patent Laid-Open No. 73497/1991 discloses a method whereby in addition to the ordinary power supply voltage terminal, another power supply voltage terminal is provided for supplying an erasing and programming voltage. Further, Japanese Patent Laid-Open No. 73497/1991 describes a method that provides a boost circuit in the chip to generate an erasing and programming voltage Vpp.